Embodiments of the inventive concept relate to a semiconductor device and a fine patterning method for semiconductor devices, and in particular, to a method of forming fine interconnection patterns that include a contact pad, a method of fabricating a semiconductor device using the same, and a semiconductor device fabricated thereby.
In order to realize a highly-integrated semiconductor device, methods of forming fine patterns may be used. For example, to form more devices per a given area, the size of each pattern should be as small as possible. In other words, a pattern should be formed in such a way that the pitch of the pattern or a sum of a width of each element of the pattern and a space between adjacent elements of the pattern is reduced. However, such approaches may be limited when the resolution of the applicable photolithography process is stretched to the limit. For example, in the case where interconnection lines are formed using a double pattern technology DPT process, there may be technical difficulties in obtaining sufficient contact area between contact plugs used as connection nodes between an external circuit and interconnection lines. For example, a cell bit-line (BL) can be connected to a direct contact (DC), which may serve as a connection node to a sense amplifier (S/A), but may have insufficient contact area. This may lead to an increase in electric resistance of the interconnection line.